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1 ? fn8108.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x28hc256 256k, 32k x 8 bit 5 volt, byte alterable eeprom features ? access time: 70ns ? simple byte and page write ?single 5v supply ? no external high voltages or v pp control circuits ?self-timed ?no erase before write ?no complex programming algorithms ?no overerase problem ? low power cmos ?active: 60ma ?standby: 500a ? software data protection ?protects data against system level inadvertent writes ? high speed page write capability ? highly reliable direct write ? cell ?endurance: 1,000,000 cycles ?data retention: 100 years ? early end of write detection ?data polling ?toggle bit polling ? pb-free plus anneal available (rohs compliant) description the x28hc256 is a second generation high perfor- mance cmos 32k x 8 eeprom. it is fabricated with intersil?s proprietar y, textured poly floating gate tech- nology, providing a highly reliable 5 volt only nonvola- tile memory. the x28hc256 supports a 128-byte page write opera- tion, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. the x28hc256 also features data polling and toggle bit polling, two methods of providing early end of write detection. the x28hc256 also supports the jedec standard software data pro- tection feature for protecti ng against inadvertent writes during power-up and power-down. endurance for the x28hc256 is specified as a mini- mum 1,000,000 write cycles per byte and an inherent data retention of 100 years. block diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 256kbit eeprom array i/o 0 ?i/o 7 data inputs/outputs ce oe v cc v ss a 0 ?a 14 we address inputs data sheet may 17, 2006
2 fn8108.1 may 17, 2006 ordering information part number part marking access time (ns) temp. range (c) package pkg. dwg. # x28hc256di-15 x28hc256di-15 150 -40 to +85 28 ld cerdip (520 mils) x28hc256dm-15 x28hc256dm-15 -55 to +125 28 ld cerdip (520 mils) x28hc256dmb-15 x28hc256dmb-15 mil-std-883 28 ld cerdip (520 mils) x28hc256emb-15 x28hc256emb-15 mil-std-883 32 ld lcc (458 mils) x28hc256fmb-15 x28hc256fmb-15 mil-std-883 28 ld flatpack (440 mils) x28hc256j-15* x28hc256j-15 0 to +70 32 ld plcc n32.45x55 x28hc256jz-15* (note) x28hc256j-15 z 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-15* x28hc256ji-15 -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-15* (note) x28hc256ji-15 z -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256jm-15* x28hc256jm-15 -55 to +125 32 ld plcc n32.45x55 x28hc256ki-15 x28hc256ki-15 -40 to +85 28 ld pga g28.550x650a x28hc256km-15 x28hc256km-15 -55 to +125 28 ld pga g28.550x650a x28hc256kmb-15 x28hc256kmb-15 mil-std-883 28 ld pga g28.550x650a x28hc256p-15 x28hc256p-15 0 to +70 28 ld pdip e28.6 x28hc256pz-15 (note) x28hc256p-15 z 0 to +70 28 ld pdip (pb-free)** e28.6 X28HC256PI-15 X28HC256PI-15 -40 to +85 28 ld pdip e28.6 X28HC256PIz-15 (note) X28HC256PI-15 z -40 to +85 28 ld pdip (pb-free)** e28.6 x28hc256pm-15 x28hc256pm-15 -55 to +125 28 ld pdip e28.6 x28hc256si-15* x28hc256si-15 -40 to +85 28 ld soic (300 mil) mdp0027 x28hc256sm-15 x28hc256sm-15 -55 to +125 28 ld soic (300 mil) mdp0027 x28hc256d-12 x28hc256d-12 120 0 to +70 28 ld cerdip (520 mils) x28hc256di-12 x28hc256di-12 -40 to +85 28 ld cerdip (520 mils) x28hc256dm-12 x28hc256dm-12 -55 to +125 28 ld cerdip (520 mils) x28hc256dmb-12 x28hc256dmb-12 mil-std-883 28 ld cerdip (520 mils) x28hc256ei-12 x28hc256ei-12 -40 to +85 32 ld lcc (458 mils) x28hc256em-12 x28hc256em-12 -55 to +125 32 ld lcc (458 mils) x28hc256emb-12 x28hc256emb-12 mil-std-883 32 ld lcc (458 mils) x28hc256fmb-12 x28hc256fmb-12 mil-std-883 28 ld flatpack (440 mils) x28hc256j-12* x28hc256j-12 0 to +70 32 ld plcc n32.45x55 x28hc256jz-12* (note) x28hc256j-12 z 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-12* x28hc256ji-12 -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-12* (note) x28hc256ji-12 z -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256ki-12 x28hc256ki-12 -40 to +85 28 ld pga g28.550x650a x28hc256km-12 x28hc256km-12 -55 to +125 28 ld pga g28.550x650a x28hc256kmb-12 x28hc256kmb-12 mil-std-883 28 ld pga g28.550x650a x28hc256p-12 x28hc256p-12 0 to +70 28 ld pdip e28.6 x28hc256pz-12 (note) x28hc256p-12 z 0 to +70 28 ld pdip (pb-free)** e28.6 X28HC256PI-12 X28HC256PI-12 -40 to +85 28 ld pdip e28.6 X28HC256PIz-12 (note) X28HC256PI-12 z -40 to +85 28 ld pdip (pb-free)** e28.6 x28hc256
3 fn8108.1 may 17, 2006 x28hc256s-12* x28hc256s-12 120 0 to +70 28 ld soic (300 mils) mdp0027 x28hc256sz-12 (note) x28hc256s-12 z 0 to +70 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256si-12* x28hc256si-12 -40 to +85 28 ld soic (300 mils) mdp0027 x28hc256siz-12 (note) x28hc256si-12 z -40 to +85 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256sm-12* x28hc256sm-12 -55 to +125 28 ld soic (300 mils) mdp0027 x28hc256d-90 x28hc256d-90 90 0 to +70 28 ld cerdip (520 mils) x28hc256di-90 x28hc256di-90 -40 to +85 28 ld cerdip (520 mils) x28hc256dm-90 x28hc256dm-90 -55 to +125 28 ld cerdip (520 mils) x28hc256dmb-90 x28hc256dmb-90 mil-std-883 28 ld cerdip (520 mils) x28hc256em-90 x28hc256em-90 -55 to +125 32 ld lcc (458 mils) x28hc256emb-90 x28hc256emb-90 mil-std-883 32 ld lcc (458 mils) x28hc256fi-90 x28hc256fi-90 -40 to +85 28 ld flatpack (440 mils) x28hc256fm-90 x28hc256fm-90 -55 to +125 28 ld flatpack (440 mils) x28hc256fmb-90 x28hc256fmb-90 mil-std-883 28 ld flatpack (440 mils) x28hc256j-90* x28hc256j-90 0 to +70 32 ld plcc n32.45x55 x28hc256jz-90* (note) x28hc256j-90 z 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-90* x28hc256ji-90 -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-90* (note) x28hc256ji-90 z -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256jm-90* x28hc256jm-90 -55 to +125 32 ld plcc n32.45x55 x28hc256km-90 x28hc256km-90 -55 to +125 28 ld pga g28.550x650a x28hc256kmb-90 x28hc256kmb-90 mil-std-883 28 ld pga g28.550x650a x28hc256p-90 x28hc256p-90 0 to +70 28 ld pdip e28.6 x28hc256pz-90 (note) x28hc256p-90 z 0 to +70 28 ld pdip (pb-free)** e28.6 X28HC256PI-90 X28HC256PI-90 -40 to +85 28 ld pdip e28.6 X28HC256PIz-90 (note) X28HC256PI-90 z -40 to +85 28 ld pdip (pb-free)** e28.6 x28hc256s-90* x28hc256s-90 0 to +70 28 ld soic (300 mils) mdp0027 x28hc256si-90* x28hc256si-90 -40 to +85 28 ld soic (300 mils) mdp0027 x28hc256siz-90 (note) x28hc256si-90 z -40 to +85 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256dmb-70 x28hc256dmb-70 70 mil-std-883 28 ld cerdip (520 mils) x28hc256ji-20 x28hc256ji-20 200 -40 to +85 32 ld plcc n32.45x55 x28hc256si-20t1 200 -40 to +85 28 ld soic (300 mils) tape and reel mdp0027 *add "t1" suffix for tape and reel. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended fo r use in reflow solder proces sing applications. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking access time (ns) temp. range (c) package pkg. dwg. # x28hc256
4 fn8108.1 may 17, 2006 pin configuration pin descriptions addresses (a 0 -a 14 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power con- sumption is reduced. output enable (oe ) the output enable input controls the data output buff- ers, and is used to initiate read operations. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x28hc256 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28hc256. pin names a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28hc256 plastic dip cerdip flat plastic soic a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 ce i/o 7 i/o 6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 lcc plcc a 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 (top view) a 12 a 14 nc v cc we a 13 nc x28hc256 11 i/o 0 10 a 0 14 v ss 9 a 1 8 a 2 7 a 3 6 a 4 5 a 5 2 a 12 28 v cc 12 i/o 1 13 i/o 2 15 i/o 3 4 a 6 3 a 7 1 16 i/o 4 20 ce 22 oe 24 a 9 17 i/o 5 27 we 19 i/o 7 21 a 10 23 a 11 25 a 8 18 i/o 6 26 a 13 (bottom view) pga a 14 x28hc256 symbol description a 0 -a 14 address inputs i/o 0 -i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect x28hc256
5 fn8108.1 may 17, 2006 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this tw o line control architecture eliminates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28hc256 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automati cally continue to comple- tion, typically within 3ms. page write operation the page write feature of the x28hc256 allows the entire memory to be written in typically 0.8 seconds. page write allows up to one hundred twenty-eight bytes of data to be cons ecutively written to the x28hc256, prior to the commencement of the internal programming cycle. the host can fetch data from another device within the sy stem during a page write operation (change the source address), but the page address (a 7 through a 14 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the in itial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. each su ccessive byte load cycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the internal automatic program- ming cycle will commence. ther e is no page write win- dow limitation. effectivel y the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. write operation status bits the x28hc256 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. figure 1. status bit assignment data polling (i/o 7 ) the x28hc256 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a sim- ple bit test operation to det ermine the status of the x28hc256. this eliminates additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read t he last byte written will pro- duce the complement of that data on i/o 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). once the pro- gramming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28hc256 also provides another method for determining when the internal write cycle is complete. during the internal programming cycle i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will ce ase, and the device will be accessible for additional read and write operations. 5 tb dp 43210 i/o reserved toggle bit data polling x28hc256
6 fn8108.1 may 17, 2006 data polling i/o 7 figure 2. data polling bus sequence figure 3. data polling software flow data polling can effectively ha lve the time for writing to the x28hc256. the timing diagram in figure 2 illus- trates the sequence of events on the bus. the soft- ware flow diagram in figu re 3 illustrates one method of implementing the routine. ce oe we i/o 7 x28hc256 ready last write high z v ol v ih a 0 ?a 14 an an an an an an v oh an write data save last data and address read last address io 7 compare? x28hc256 no yes writes complete? no yes ready x28hc256
7 fn8108.1 may 17, 2006 the toggle bit i/o 6 figure 4. toggle bit bus sequence figure 5. toggle bit software flow ? the toggle bit can eliminate the chore of saving and fetching the last address and data in order to implement data polling. this can be especially helpful in an array comprised of multiple x28hc256 memories that is frequently updated. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow diagram in fi gure 5 illustrates a method for polling the toggle bit. hardware data protection the x28hc256 provides two hardware features that protect nonvolatile data from inadvertent writes. ? default v cc sense?all write func tions are inhibited when v cc is 3.5v typically. ? write inhibit?holding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. software data protection the x28hc256 offers a software-controlled data pro- tection feature. the x28hc256 is shipped from intersil with the software data protection not enabled; that is, the device will be in th e standard operating mode. in this mode data should be protected during power- up/down operations through the use of external cir- cuits. the host would then have open read and write access of the device once v cc was stable. the x28hc256 can be automatically protected during power-up and power-down (without the need for exter- nal circuits) by employing the software data protection feature. the internal softwa re data protection circuit is enabled after the first write operation, utilizing the soft- ware algorithm. this circ uit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28hc256 is also protected from inadvert ent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. ce oe we x28c512/513 last write i/o 6 high z * * v oh v ol ready * i/o 6 beginning and ending state of i/o 6 will vary. compare x28c256 no yes ok? compare accum with addr n load accum from addr n last write ready yes x28hc256
8 fn8108.1 may 17, 2006 software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. refer to figure 6 and 7 for the sequence. the three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. once the page load cycle has been completed, the de vice will automatically be returned to the data protected state. software data protection figure 6. timing sequence?byte or page write figure 7. write sequence for software data protection regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the x28hc256 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issu ed the x28hc256 will be write protected during power-down and after any sub- sequent power-up. note: once initiated, the sequence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data address aaa 5555 55 2aaa a0 5555 t blc max writes ok byte or age t wc write last write data xx to any write data a0 to address 5555 write data 55 to address 2aaa write data aa to address 5555 after t wc re-enters data protected state byte to last address address optional byte/page load operation byte/page load enabled x28hc256
9 fn8108.1 may 17, 2006 resetting software data protection figure 8. reset software data protection timing sequence figure 9. write sequence for resetting software data protection in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an eeprom programmer, th e following six step algo- rithm will reset the internal protection circuit. after t wc , the x28hc256 will be in standard opera ting mode. note: once initiated, the sequence of write operations should not be interrupted. system considerations because the x28hc256 is frequently used in large memory arrays, it is prov ided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipa- tion, and eliminate the possi bility of contention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus and be used as the primary device select ion input. both oe and we would then be common among all devices in the array. for a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. because the x28hc256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause tran- sient current spikes. the magnitude of these spikes is dependent on the output capaci tive loading of the l/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be sup- pressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recom- mended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effe cts of the pc board traces. ce we standard operating mode v cc data address aaa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555 write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 after t wc , re-enters unprotected state x28hc256
10 fn8108.1 may 17, 2006 absolute maximum ratings temperature under bias x28hc256 ....................................... -10c to +85c x28hc256i, x28hc256m .............. -65c to +135c storage temperature ......................... -65c to +150c voltage on any pin with respect to v ss ........................................ -1v to +7v d.c. output current ............................................. 10ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indi- cated in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) notes: (1) typical values are for t a = 25c and nominal supply voltage. (2) v il min. and v ih max. are for reference only and are not tested. power-up timing note: (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. typ. (7) max. i cc v cc active current (ttl inputs) 30 60 ma ce = oe = v il , we = v ih , all i/o?s = open, address inputs = .4v/2.4v levels @ f = 10mhz i sb1 v cc standby current (ttl inputs) 12mace = v ih , oe = v il , all i/o?s = open, other inputs = v ih i sb2 v cc standby current (cmos inputs) 200 500 a ce = v cc - 0.3v, oe = gnd, all i/os = open, other inputs = v cc - 0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc , ce = v ih v ll (2) input low voltage -1 0.8 v v ih (2) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 6ma v oh output high voltage 2.4 v i oh = -4ma symbol parameter max. unit t pur (3) power-up to read 100 s t puw (3) power-up to write 5 ms recommended operating conditions temperature min. max. commercial 0c +70c industrial -40c +85c military -55c +125c supply voltage limits x28hc256 5v 10% x28hc256
11 fn8108.1 may 17, 2006 capacitance t a = +25c, f = 1mhz, v cc = 5v endurance and data retention a.c. conditions of test mode selection equivalent a.c. load circuit symbol table symbol test max. unit conditions c i/o (9) input/output capacitance 10 pf v i/o = 0v c in (9) input capacitance 6 pf v in = 0v parameter min. max. unit endurance 1,000,000 cycles data retention 100 years input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v ce oe we mode i/o power l l h read d out active lhl write d in active h x x standby and write inhibit high z standby x l x write inhibit ? ? x x h write inhibit ? ? 5v 1.92k 30pf output 1.37k waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x28hc256
12 fn8108.1 may 17, 2006 a.c. characteristics (over the recommended operating condit ions, unless otherwise specified.) read cycle limits read cycle notes: (4) t lz min., t hz , t olz min. and t ohz are periodically sampled and not 100% tested, t hz and t ohz are measured with cl = 5pf, from the point when ce , oe return high (whichever occurs first) to the time when the outputs are no longer driven. (5) for faster 256k products, refer to x28vc256 product line. symbol parameter x28hc256-70 x28hc256-90 x28hc256-12 x28hc256-15 unit min. max. min. max. min. max. min. max. t rc (5) read cycle time 70 90 120 150 ns t ce (5) chip enable access time 70 90 120 150 ns t aa (5) address access time 70 90 120 150 ns t oe output enable access time 35 40 50 50 ns t lz (4) ce low to active output 0 0 0 0 ns t olz (4) oe low to active output 0 0 0 0 ns t hz (4) ce high to high z output 35 40 50 50 ns t ohz (4) oe high to high z output 35 40 50 50 ns t oh output hold from address change 0 0 0 0 ns t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid x28hc256
13 fn8108.1 may 17, 2006 write cycle limits notes: (6) typical values are for t a = 25c and nominal supply voltage. (7) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. (8) t wph and t dw are periodically sampled and not 100% tested. we controlled write cycle symbol parameter min. typ. (6) max. unit t wc (7) write cycle time 3 5 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 50 ns t oes oe high setup time 0 ns t oeh oe high hold time 0 ns t wp we pulse width 50 ns t wph (8) we high recovery (page write only) 50 ns t dv data valid 1s t ds data setup 50 ns t dh data hold 0 ns t dw (8) delay to next write after polling is true 10 s t blc byte load cycle 0.15 100 s address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp x28hc256
14 fn8108.1 may 17, 2006 ce controlled write cycle page write cycle notes: (9) between successive byte wr ites within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. (10)the timings shown above are unique to page write operations. i ndividual byte load operations within the page write must con form to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t ds t dh t ch ce we oe data in data out high z data valid t cw we oe (9) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address (10) i/o *for each successive write with in the page write operation, a 7 ?a 15 should be the same or writes to an unknown address could occur. x28hc256
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8108.1 may 17, 2006 data polling timing diagram (11) toggle bit timing diagram (11) note: (11)polling operations are by definition read cycl es and are therefore subject to read cycle timings. address a n d in = x t wc t oeh t oes ce we oe i/o 7 t dw a n a n d out = x d out = x ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary, depending upon actual t wc . x28hc256
x28hc256 printer friendly version 256k, 32k x 8 bit; 5 volt, byte alterable eeprom datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x28hc256d-12 active comm 28 ld cerdip n/a 33.33 x28hc256d-90 active comm 28 ld cerdip n/a x28hc256di-12 active ind 28 ld cerdip n/a 28.18 x28hc256di-12c7517 active ind 28 ld cerdip n/a x28hc256di-15 active ind 28 ld cerdip n/a 22.22 x28hc256di-15c7846 active ind 28 ld cerdip n/a x28hc256di-15c7856 active ind 28 ld cerdip n/a x28hc256di-15c7921 active ind 28 ld cerdip n/a x28hc256di-90 active ind 28 ld cerdip n/a 30.00 x28hc256dm-12 active mil 28 ld cerdip n/a x28hc256dm-15 active mil 28 ld cerdip n/a 29.41 x28hc256dm-90 active mil 28 ld cerdip n/a 47.06 x28hc256dmb-12 active mil 28 ld cerdip n/a 41.18 x28hc256dmb-15 active mil 28 ld cerdip n/a 35.29 x28hc256dmb-90 active mil 28 ld cerdip n/a 52.94 x28hc256ei-12 active ind 32 ld clcc n/a 94.44 x28hc256em-90 active mil 32 ld lcc n/a 76.47 x28hc256emb-12 active mil 32 ld lcc n/a 80.14 x28hc256emb-15 active mil 32 ld lcc n/a 55.29 x28hc256emb-90 active mil 32 ld lcc n/a 82.35 x28hc256fi-90 active ind 28 ld flatpack n/a x28hc256fm-90 active mil 28 ld flatpack n/a x28hc256fmb-12 active mil 28 ld flatpack n/a 103.11 x28hc256fmb-15 active mil 28 ld flatpack n/a 96.47 x28hc256fmb-90 active mil 28 ld flatpack n/a 161.11 x28hc256j-12 active comm 32 ld plcc 3 4.74 x28hc256j-12t1 active comm 32 ld plcc t+r 3 4.74 x28hc256j-15 active comm 32 ld plcc 3 3.89 x28hc256j-15t1 active comm 32 ld plcc t+r 3 3.89 x28hc256j-15t2 active comm 32 ld plcc t+r 3 3.89 x28hc256j-90 active comm 32 ld plcc 3 11.11 x28hc256j-90t1 active comm 32 ld plcc t+r 3 11.11 x28hc256ji-12 active ind 32 ld plcc 3 7.62 x28hc256ji-12t1 active ind 32 ld plcc t+r 3 7.62
x28hc256ji-15 active ind 32 ld plcc 3 4.44 x28hc256ji-15t1 active ind 32 ld plcc t+r 3 4.44 x28hc256ji-15t2 active ind 32 ld plcc t+r 3 4.44 x28hc256ji-90 active ind 32 ld plcc 3 6.67 x28hc256ji-90t1 active mil 32 ld plcc t+r 3 6.67 x28hc256jiz-12 active ind 32 ld plcc 3 7.62 x28hc256jiz-12t1 active ind 32 ld plcc t+r 3 7.62 x28hc256jiz-15 active ind 32 ld plcc 3 4.44 x28hc256jiz-15t1 active ind 32 ld plcc t+r 3 4.44 x28hc256jiz-90 active ind 32 ld plcc 3 6.67 x28hc256jiz-90t1 active ind 32 ld plcc t+r 3 6.67 x28hc256jm-15 active mil 32 ld plcc 3 27.60 x28hc256jm-15t1 active mil 32 ld plcc t+r 3 27.60 x28hc256jm-90 active mil 32 ld plcc 3 30.59 x28hc256jm-90t1 active mil 32 ld plcc t+r 3 30.59 x28hc256jm-90t2 active mil 32 ld plcc t+r 3 30.59 x28hc256jz-12 active comm 32 ld plcc 3 4.74 x28hc256jz-12t1 active comm 32 ld plcc t+r 3 4.74 x28hc256jz-15 active comm 32 ld plcc 3 3.89 x28hc256jz-15t1 active comm 32 ld plcc t+r 3 3.89 x28hc256jz-90 active comm 32 ld plcc 3 11.11 x28hc256jz-90t1 active comm 32 ld plcc t+r 3 11.11 x28hc256ki-12 active ind 28 ld pga n/a 18.72 x28hc256ki-15 active ind 28 ld pga n/a 18.33 x28hc256km-12 active mil 28 ld pga n/a 35.29 x28hc256km-15 active mil 28 ld pga n/a 32.94 x28hc256km-90 active mil 28 ld pga n/a 39.41 x28hc256kmb-12 active mil 28 ld csp n/a 58.82 x28hc256kmb-15 active mil 28 ld csp n/a 52.94 x28hc256kmb-90 active mil 28 ld csp n/a 82.35 x28hc256p-12 active comm 28 ld pdip n/a 6.67 x28hc256p-15 active comm 28 ld pdip n/a 5.56 x28hc256p-90 active comm 28 ld pdip n/a 8.33 X28HC256PI-12 active ind 28 ld pdip n/a 7.78 X28HC256PI-15 active ind 28 ld pdip n/a 6.11 X28HC256PIz-12 active ind 28 ld pdip n/a 7.78 X28HC256PIz-15 active ind 28 ld pdip n/a 6.11 X28HC256PIz-90 active ind 28 ld pdip n/a 17.71 x28hc256pm-15 active mil 28 ld pdip n/a 12.20 x28hc256pz-12 active comm 28 ld pdip n/a 6.67 x28hc256pz-15 active comm 28 ld pdip n/a 5.56
x28hc256pz-90 active comm 28 ld pdip n/a 8.33 x28hc256s-12 active comm 28 ld soic 3 9.14 x28hc256s-12t1 active comm 28 ld soic t+r 3 9.14 x28hc256s-90 active comm 28 ld soic 3 10.83 x28hc256s-90t1 active comm 28 ld soic t+r 3 10.83 x28hc256si-12 active ind 28 ld soic 3 10.00 x28hc256si-12t1 active ind 28 ld soic t+r 3 10.00 x28hc256si-15 active ind 28 ld soic 3 5.56 x28hc256si-15t1 active ind 28 ld soic t+r 3 5.56 x28hc256si-20t1 active ind 28 ld soic t+r 3 x28hc256si-90 active ind 28 ld soic 3 11.11 x28hc256si-90t1 active ind 28 ld soic t+r 3 11.11 x28hc256siz-12 active ind 28 ld soic 3 10.00 x28hc256siz-90 active ind 28 ld soic 3 11.11 x28hc256sm-12 active mil 28 ld soic 3 18.29 x28hc256sm-12t1 active mil 28 ld soic t+r 3 18.29 x28hc256sm-12t2 active mil 28 ld soic t+r 3 x28hc256sm-15 active mil 28 ld soic 3 x28hc256sz-12 active comm 28 ld soic 3 9.14 x28hc256em-12 coming soon comm 32 ld lcc n/a X28HC256PI-90 coming soon ind 28 ld pdip n/a x28hc256di-15c7871 inactive ind 28 ld cerdip n/a x28hc256dmb-70 inactive mil 28 ld cerdip n/a x28hc256ei inactive ind 32 ld clcc n/a x28hc256ji-20 inactive ind 32 ld plcc 3 4.11 X28HC256PI inactive ind 28 ld pdip n/a x28hc256si inactive ind 28 ld soic 5 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the x28hc256 is a second generation high performance cmos 32k x 8 eeprom. it is fabricated with intersil?s proprietary, textured poly floating gate technology, providing a highly reliable 5v only nonvolatile memory. the x28hc256 supports a 128-byte page write operation, effectively providing a 24 s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. the x28hc256 also features data polling and toggle bit polling, two methods of providing early end of write detection. the x28hc256 also supports the jedec standard software data protection feature for protecting against inadvertent writes during power-up and power-down. endurance for the x28hc256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years. key f eatures access time: 70ns simple byte and page write single 5v supply no external high voltages or v p-p control circuits self-timed no erase before write no complex programming algorithms
no overerase problem low power cmos active: 60ma standby: 500 a software data protection protects data against system level inadvertent writes high speed page write capability highly reliable direct write? cell endurance: 1,000,000 cycles data retention: 100 years early end of write detection data polling toggle bit polling pb-free plus anneal available (rohs compliant) related documentation datasheet(s): 256k, 32k x 8 bit; 5 volt, byte alterable eeprom technical homepage: digital ics parametric data organization 32kx8-bit access time (ns) 70 active current max. (ma) 60 standby current max. ( a) 500 related devices parametric table x28c010 5v, byte alterable e 2 prom x28c512 5v, byte alterable eeprom x28c513 5v, byte alterable eeprom x28hc64 64k, 8k x 8 bit; 5 volt, byte alterable eeprom about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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